1. Technical Field
The present disclosure relates to an electrically erasable and programmable (EEPROM) memory and to a method for programming and erasing the memory.
2. Description of the Related Art
In conventional EEPROM memories, memory cells are grouped in words of fixed length, for example 8, 16, or 32 bits. Each word comprises a corresponding number of memory cells, which are collectively erasable and individually programmable.
FIG. 1 shows the structure of a word Wi,k in a conventional EEPROM memory array MA0. The word Wi,k comprises J memory cells MC and a control gate transistor CTi,k. Each memory cell comprises a select transistor ST and a floating gate transistor FGT. The select transistor ST has a drain D connected to a bitline BLj, a gate G connected to a first wordline WL1i, and a source S connected to a drain D of the floating gate transistor. The floating gate transistor FGT has a gate G connected to a control gate line GLi,k, and a source S connected to a source line SLi. The control gate transistor CTi,k has a drain D connected to a column select line CLk, and a source S connected to the control gate line GLi,k.
Erasing or programming of memory cells is performed by injecting or extracting electrical charges in or from the floating gate of the floating gate transistors FGT by tunnel effect, also known as the Fowler Nordheim effect. To this end, a high voltage Vpp is applied to the gate of the transistors FGT through the control gate transistor CTi,k or to the drain of the transistors FGT through the select transistor ST.
It is known from U.S. Pat. No. 6,934,192, which is incorporated by reference herein in its entirety, that the select transistor ST of a memory cell may suffer from a gate oxide breakdown due to deficiencies of the manufacturing process and/or an erase/program stress. It has been demonstrated that such breakdown may not only prevent erase, program, and read operations from being performed on the defective memory cell, but may also prevent other memory cells from being correctly erased or programmed. The above-mentioned patent brings to light and addresses this problem by providing a second wordline WL2i to which the gate of the control gate transistor CTi,k is connected. This allows the voltage applied to the gates of the select transistors ST through the first wordline WL1i to be different from the voltage applied to the control gate transistor CTi,k through the second wordline WL2i. The above-mentioned patent also proposes to limit the current flowing through a bitline BLj connected to a select transistor ST with a gate oxide breakdown.